1. Field of the Invention
The present invention relates generally to electrical devices and, more particularly, to the testing of integrated circuit devices.
2. Related Art
Semiconductor or integrated circuit devices have continually evolved to provide improvements such as miniaturization, reduced power consumption, reduced cost, and increased speed. One consequence of the rapidly increasing speed (e.g., increasing data rate) of semiconductor devices is that adequate testing of the semiconductor devices becomes difficult and expensive. For example, integrated circuits now routinely operate at data rates above 100 MHz. For testing purposes, such data rates may require expensive, specialized automated test equipment.
When data rates reach or exceed 400 MHz, current commercially available automated test equipment may fail to detect the data with sufficient accuracy in order to perform the desired testing. In particular, during testing, signal parameters such as voltage, current, and timing or skew must be precisely controlled and monitored, for example, using currently employed techniques and systems, such as special load boards and handler designs. As data rates continue to increase, these currently employed techniques and systems, taken alone, will not be adequate to perform high-speed testing. As a result, there is a need for improved methods and techniques for testing integrated circuit devices.
In accordance with some embodiments of the present invention, circuitry is provided that latches and extends each cycle of integrated circuit test data for multiple cycles (i.e., n cycles). A low-frequency integrated circuit tester can then accurately detect the test data at a fraction of the data rate or data transfer speed of the integrated circuit (e.g., the data rate multiplied by 1/n). To eliminate the increased test time resulting from the reduced data rate, the test data may also be compressed.
In accordance with one embodiment of the present invention, an integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.
In accordance with another embodiment of the present invention, a method of testing an integrated circuit device includes receiving test data at a first clock rate internal to the integrated circuit device and comparing the received test data to expected test data values. The method further includes staggering the comparison of the test data to the expected test data values and providing an output signal to external integrated circuit test equipment at a second clock rate that is slower than the first clock rate. The output signal indicates a result of the comparison.
In accordance with another embodiment, an integrated circuit device system includes a first integrated circuit device to be tested that outputs test data at a first clock rate internal to the first integrated circuit device. The system further includes a second integrated circuit device connected to the first integrated circuit device and that receives the test data from the first integrated circuit device and provides a result in response to the test data at a second clock rate that is slower than the first clock rate.
In various embodiments of the invention, circuitry and methods are provided for receiving test result data which is generated at the speed of the normal operational clock signal of the integrated circuit device, and outputting a compressed form of the test result data at the speed of a second clock signal which is slower than the normal operational clock signal. Accordingly, the integrated circuit device can be tested with test equipment that operates at a speed which is slower than the frequency of the normal operational clock signal of the device.